If an odd numbered of inverters are coupled together in a loop, a ring oscillator results if the loop gain is greater than one. In contrast, if an even number inverters are coupled together in this fashion, a latch results such as a conventional SRAM cell, which is formed from a pair of cross-coupled inverters. To form a voltage-controlled oscillator (VCO), each inverter stage in a ring oscillator is configured so that its propagation delay is responsive to a control voltage. The resulting ring-oscillator-formed VCOs are important circuit building blocks in applications such as phase locked loops. Because of their common mode noise rejection and tuning properties, differential VCOs are particularly popular in such applications.
A conventional VCO 100 is illustrated in FIG. 1 having five differential inverter stages 101. As will be discussed further with regard to FIG. 2, each differential inverter stage is configured to steer a “tail current” I from a current source responsive to its differential input voltages. The propagation delay through each differential inverter stage and hence the output frequency of a differential output signal from output nodes 110 is controlled by a control voltage, Vcntl.
FIG. 2 illustrates a typical implementation for differential inverter stages 101. A differential pair of NMOS transistors Q1 and Q2 have their drains isolated from a supply voltage node Vcc by PMOS transistors M2 and M3, respectively. Each PMOS transistor M2 and M3 has its gate controlled by the control voltage signal Vcntl such that transistors M2 and M3 act as resistors in the triode mode of operation. Thus, the magnitude of the control voltage controls the resistance through transistors M2 and M3 and hence the signal delay in each inverter stage. Each transistor M2 and M3 may thus be represented by a variable resistor of resistance R determined by the control voltage. Differential input voltages Vin+ and Vin− control the gates of transistors Q1 and Q2, whose sources are tied to a current source driving the tail current I. The drains of transistors Q2 and Q1 tie to the nodes for differential output voltages Vout+ and Vout−, respectively. Because transistors Q1 and Q2 form a differential pair, virtually the entire tail current I will steer through the transistor whose gate voltage is higher than a threshold voltage multiple as compared to the remaining gate voltage. For example, if Vin+ is sufficiently higher than Vin−, the tail current steers through Q1.
It can be shown that the output frequency of voltage-controlled oscillator 100 is proportional to the inverse of the propagation delay τ for each inverter stage 101. In general, the delay is proportional to resistance R through transistors M2 and M3. However, this delay is also affected by semiconductor process variations that, for example, affect the balance between n-channel and p-channel transistors in a particular wafer. A customer of a semiconductor foundry can never guarantee, a priori, what particular process corner will be used to manufacture a given batch of wafers. Thus, the output frequency of a VCO in response to a certain control voltage level cannot be predicted until it is known what semiconductor process variation (fast or slow corner) was used in its manufacture. In addition, temperature variations will also affect the frequency response of a VCO. Various compensation circuits have been developed to address VCO sensitivity to temperature and process variations. However, these circuits tend to be complex and thus add considerably to manufacturing cost.
Accordingly, there is a need in the art for an improved VCO that automatically compensates for process and temperature variations.